TC1796
System Units (Vol. 1 of 2)
Program Memory Unit
User’s Manual 7-11 V2.0, 2007-07
PMU, V2.0
7.2.4 Basic Flash Operating Modes
The basic operating modes are Flash-bank specific. Generally, there are two basic
operating modes of the Flash banks:
• Read Mode (optionally with Page Mode activated)
• Command Mode
Since the TC1796 Flash array has three autonomous Flash banks, one PFLASH bank
and two DFLASH banks, parallel write command execution (programming one bank
while erasing the other bank) is supported for the two DFLASH banks, but not for the
PFLASH bank and one DFLASH bank.
Flash register accesses are independent of the operating modes and allowed in any
state. After any reset operation, the Flash banks are in Read Mode.
The following sections describe the operating modes specifically for the PFLASH. If
there is any difference for the DFLASH, additional hints are given.
7.2.4.1 Read Mode
A Flash bank enters or remains in the standard operating mode, the Read Mode
• After a Reset-to-Read command, if no programming or erase operation is active
• After any completed Erase command
• After a completed Write Page (programming) command
• After every other completed command execution
• During ramp-up time after the deactivation of any reset
• After incorrect address/data values or wrong command sequence
• After incorrect requests (password failure) to program or erase a locked sector
• After an incorrect write access to a read-protected Flash memory
In Read Mode, command sequences are allowed. The Read Mode remains active until
the last cycle of a command sequence is executed. In case of a write or erase command,
Read Mode is terminated at the end of the command sequence.
If Page Mode is active in Read Mode, the page assembly buffer can be loaded (written)
with data for the next write page (program) command while Flash read operations occur
in parallel. As a special case, it is even allowed to place instructions in the PFLASH, used
to load the page assembly buffer or to write command sequences to the DFLASH.
Read accesses from a Flash array are always 64-bit aligned. During these 64-bit wide
read accesses from the Flash array, automatic error detection and - if a single-bit error
is detected - an error correction can be executed. Bit errors are reported by separate
single-bit error flags and double-bit error flags that are located in the FLASH_FSR
register. Setting of single-bit or/and double-bit error flags can generate a Flash interrupt
if enabled (see Page 7-37). In case of a double-bit error, the CPU is interrupted by a bus
error trap per default which further results in an interrupt from the PLMB Bus Control Unit
PBCU.
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