TC1796
System Units (Vol. 1 of 2)
System Control Unit
User’s Manual 5-51 V2.0, 2007-07
SCU, V2.0
read back. The ENOUTn bits determine whether or not the logic level state as defined
by the bits in the SCU_PTDATn register is output to the pad/pin.
5.9.1 Pad Test Mode Enabling
To enable the pad test mode, the following two-word write sequence must be executed:
1. Writing SCU_PTCON with lock code PTMLC = 5A
H
2. Writing SCU_PTCON with lock code PTMLC = A5
H
. After this write operation pad
test mode is enabled, as indicated by PTMEN = 1. Bits ENOUTn and RDSSn
determine the requested pad test mode configuration (enable, input selection).
When pad test mode is enabled, the test mode configuration (as defined through
ENOUTn and RDSSn) can be changed without leaving the pad test mode by writing
SCU_PTCON with new values for bits ENOUTn and RDSSn and PTMLC = A5
H
. In pad
test mode, any other write operation to SCU_PTCON with lock code PTMLC not equal
to A5
H
terminates the pad test mode.
After pad test mode has been enabled via the two-word write operation to SCU_PTCON,
it can be disabled again by any reset operation or a write operation to SCU_PTCON.
5.9.2 Pad Test Mode Registers
The pad test mode control logic contains five registers.
Table 5-8 Pad Test Mode Registers
Register Short Name Register Long Name Description
see
SCU_PTCON SCU Pad Test Control Register Page 5-52
SCU_PTDAT0 SCU Pad Test Data Register 0 Page 5-53
SCU_PTDAT1 SCU Pad Test Data Register 1 Page 5-54
SCU_PTDAT2 SCU Pad Test Data Register 2 Page 5-55
SCU_PTDAT3 SCU Pad Test Data Register 3 Page 5-56
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