TC1796
System Units (Vol. 1 of 2)
Clock System and Control
User’s Manual 3-42 V2.0, 2007-07
Clock, V2.0
3.4.1 System Clock Fractional Divider Register
SCU_SCLKFDR
SCU System Clock Fractional Divider Register
(F000000C
H
) Reset Value: 0000 0000
H
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DIS
CLK
EN
HW
SUS
REQ
SUS
ACK
0 RESULT
rwh rw rh rh r rh
1514131211109876543210
DM SC SM 0 STEP
rw rw rw r rw
Field Bits Type Description
STEP [9:0] rw Step Value
Reload or addition value for RESULT.
SM 11 rw Suspend Mode
SM selects granted or immediate suspend mode.
DM [15:14] rw Divider Mode
DM selects normal or fractional divider mode.
SC [13:12] rw Suspend Control
SC determines the behavior of the fractional divider
in suspend mode.
RESULT [25:16] rh Result Value
Bit field for the addition result.
SUSACK 28 rh Suspend Mode Acknowledge
Indicates state of SPNDACK signal.
SUSREQ 29 rh Suspend Mode Request
Indicates state of SPND signal.
ENHW 30 rw Enable Hardware Clock Control
No function for SYSCLK generation. Should be
written with 0, will read back the last value written
DISCLK 31 rwh Disable Clock
Makes it possible to disable the clock generation
independently of the setting of the other functions
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