TC1796
Peripheral Units (Vol. 2 of 2)
General Purpose Timer Array (GPTA)
User’s Manual 24-7 V2.0, 2007-07
GPTA, V2.0
24.2.1 GTPA Units
Each of the General Purpose Timer Arrays GPTA0 and GPTA1 (Figure 24-2) is split into
a Clock Generation Unit (CGU) and a Signal Generation Unit (SGU):
•The Clock Generation Unit (see Page 24-8) allows a preprocessing of the input
signals using filter, timer, capture, compare and enhanced digital PLL Modules:
– The Filter and Prescaler Cells (FPC) provide input noise filtering (Immediate
Debounce and Delayed Debounce) and may also work as prescalers for the GPTA
module clock and external signals.
– The Phase Discrimination Logic (PDL) may take the outputs of the FPCs to
decode phase encoded signals from a position and rotation direction sensor
system.
– The Duty Cycle Measurement Cells (DCM) provide signal measurement
capabilities (timer plus capture register, single and double capture on rising and
falling edges or both) as well as missing pulse detection/reconstruction functions.
– The Digital Phase Locked Loop (Digital PLL) is intended to generate a higher
resolution clock from the values measured by DCM cells. Any arbitrary
multiplication factor between 1 and 65535 is supported and may be changed from
input clock period to input clock period.
– The Clock Distribution Unit (CDU) provides all LTCs and GTs with a variety of
different clock signals. It is equipped with GPTA module clock prescalers and
multiplexers supporting alternate clock sources.
The original signals and all outputs of the preprocessing units are distributed to the
Global Timers and LTCs via the clock bus.
•The Signal Generation Unit (see Page 24-37) provides a set of timers, capture and
compare units:
– The two 24-bit Global Timers (GT) can be individually configured as free-running
counters or as reload counters starting at a programmable value from 0
H
to
FFFFFF
H
. Each GT is equipped with a scalable greater-or-equal comparator; the
number of bits to be compared is selectable.
– The Global Timer Cell registers (GTC) are 24-bit wide. GTCs may be used as
comparators (modifying the logical state of a related output port pin), or as capture
units, storing the current GT0 or GT1 value on rising, falling or both signal edges
detected on a related input port pin. Several adjacent GTCs may be connected to
logical units operating on the same pin, allowing complex functions to be
implemented.
– The Local Timer Cell registers (LTC) are 16-bit wide. 63 LTCs can be configured
to operate in one of four different modes: free-running or resettable counter,
capture or compare unit. Adjacent cells can be combined to operate on the same
pin, thus generating complex waveforms. One LTC (LTC63) can be used for
special compare modes.
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