TC1796
System Units (Vol. 1 of 2)
System Timer
User’s Manual 15-1 V2.0, 2007-07
STM, V2.0
15 System Timer
15.1 Overview
This chapter describes the System Timer (STM). The TC1796’s STM is designed for
global system timing applications requiring both high precision about long periods. The
STM has the following features:
• Free-running 56-bit counter
• All 56 bits can be read synchronously
• Different 32-bit portions of the 56-bit counter can be read synchronously
• Flexible interrupt generation based on compare match with partial STM content
• Driven by max. 75 MHz clock (= f
SYS
, default after reset = f
SYS
/2)
• Counting starts automatically after a reset operation
• STM is reset by:
– Watchdog reset
– Software reset (RST_REQ.RRSTM must be set)
– Power-on reset
• STM (and clock divider STM_CLC.RMC) is not reset at a hardware reset
(HDRST = 0)
• STM can be halted in debug/suspend mode (via STM_CLC register)
Special STM register semantics provide synchronous views of the entire 56-bit counter,
or 32-bit subsets at different levels of resolution.
The maximum clock period is 2
56
× f
STM
. At f
STM
= 75 MHz, for example, the STM counts
30.47 years before overflowing. Thus, it is capable of continuously timing the entire
expected product life-time of a system without overflowing.
15.2 Operation
The STM is an upward counter, running either at the system clock frequency f
SYS
or at a
fraction of it. The STM clock frequency is f
STM
= f
SYS
/RMC with RMC = 0-7 (default after
reset is f
STM
= f
SYS
/2, selected by RMC = 010
B
). RMC is a bit field in register STM_CLC.
In case of a power-on reset, a watchdog reset, or a software reset, the STM is reset. After
one of these reset conditions, the STM is enabled and immediately starts counting up. It
is not possible to affect the content of the STM during normal operation of the TC1796.
The timer registers can only be read but not written to.
The STM can be optionally disabled for power-saving purposes, or suspended for
debugging purposes via its clock control register. In suspend mode of the TC1796
(initiated by writing an appropriate value to STM_CLC register), the STM clock is
stopped but all registers are still readable.
Due to the 56-bit width of the STM, it is not possible to read its entire content with one
instruction. It needs to be read with two load instructions. Since the timer would continue
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