TC1796
Peripheral Units (Vol. 2 of 2)
Synchronous Serial Interface (SSC)
User’s Manual 20-48 V2.0, 2007-07
SSC, V2.1
20.3.2.1 Clock Control
The SSC modules each have two clock signals:
• f
CLC0
and f
CLC1
This is the module clock that is used inside the SSC kernel for control purposes such
as, e.g. clocking of control logic and register operations. The frequency of f
CLC0
and
f
CLC1
is always identical to the system clock frequency f
SYS
. The clock control
registers SSC0_CLC and SSC1_CLC make it possible to enable/disable
f
CLC0
and
f
CLC1
under certain conditions.
• f
SSC0
and f
SSC1
This clock is the module clock that is used in the SSC as input clock of the baud rate
generator, which finally determines the baud rate of the serial data. The fractional
divider registers SSC0_FDR and SSC1_FDR control the frequency of f
SSC0
and f
SSC1
and make it possible to enable/disable it independently of f
CLC0
and f
CLC1
.
The Baud Rate Timer Reload Register SSC0_BR and SSC1_BR define serial data
baud rate dependent from the frequency of f
SSC0
and f
SSC1
.
Figure 20-18 SSC Clock Generation
Output signal CAN_INT_O15 of the MultiCAN module can be used for external clock
enable control of the fractional divider.
MCA05793
Clock Control
Register
SSC0_CLC
f
CLC0
SSC0 Clock Generation
f
SSC0
f
SYS
Fractional Divider
Register
SSC0_FDR
Clock Control
Register
SSC1_CLC
f
CLC1
SSC1 Clock Generation
f
SSC1
Fractional Divider
Register
SSC1_FDR
SSC0 Module
Kernel
Baud Rate
Generator
SSC0_BR
SSC1 Module
Kernel
Baud Rate
Generator
SSC1_BR
MultiCAN
Module
INT_O15
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