Infineon Technologies TC1796 - 2.4.2.1 Implementation-specific CPU Slave Interface Registers

TC1796
System Units (Vol. 1 of 2)
CPU Subsystem
User’s Manual 2-14 V2.0, 2007-07
CPU, V2.0
2.4.2.1 Implementation-specific CPU Slave Interface Registers
All registers from Table 2-3 have a TC1796-specific implementation detail, the Type of
Service Control (TOS) bit/bit field. CPU_SBSRC0 is described on Page 2-19. The non-
shaded areas in the CPU_SRCn register description defines the implementation-specific
bits/bit fields.
CPU_SRCn (n = 0-3)
CPU Service Request Control Register n
(F7E0FFFC
H
-n*4
H
) Reset Value: 0000 0000
H
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
r
1514131211109876543210
SET
R
CLR
R
SRR SRE 0 TOS 0 SRPN
w w rh rw r rw r rw
Field Bits Type Description
TOS 10 rw Type of Service Control
0
B
Service Provider = CPU
1
B
Service Provider = PCP
011rReserved
Read as 0; should be written with 0.