TC1796
System Units (Vol. 1 of 2)
Peripheral Control Processor (PCP)
User’s Manual 11-30 V2.0, 2007-07
PCP, V2.0
• If ST = 1 is specified bit R7.CEN (Channel Enable) is cleared (i.e. the channel is
disabled).
• If EP = 0 is specified or PCP_CS.RCB = 1 (Channel Restart Mode has been
selected), the PCP program counter to be saved to context location CR7.PC is set to
the appropriate channel entry table address. If EP = 1 is specified and PCP_CS.RCB
= 1 (Channel Resume Mode has been selected), the PCP program counter to be
saved to context location CR7.PC is set to the address of the instruction immediately
following the EXIT instruction.
• If INT = 1 is specified and the specified condition cc_B is True, then an interrupt
request is raised according to the SRPN value held in R6.SRPN. The interrupt is
asserted via one of the PCP_SRCx registers, where x is determined by the
combination of the value of R6.TOS and the list of free entries. This allows the
conditional creation of a service request to the CPU or PCP with the SRPN value
indicated in register R6.SRPN.
• The channel program’s context (including all register modifications caused within this
EXIT sequence) is saved to the appropriate region in the PRAM Context Save Area.
Depending on the value of PCP_CS.CS, either a Full, Small, or Minimum Context
save is used.
Special care needs to be taken to optimize the number of clock cycles required to
perform a Context Save. During a Context Save, the PCP Processor Core needs only to
save those registers that have been written since the last Context Restore was
performed.
Note: Particular attention must be paid to the values of R6 and R7 prior to execution of
the EXIT instruction. When posting an interrupt request, the user must ensure that
R6.SRPN and R6.TOS contain the correct values to generate the required
interrupt request. When using the Outer Loop Counter (CNT1), the user must
ensure that the value in R6.CNT1 will provide the required function. When using
interrupt priority management, the user must ensure that R6.CPPN contains the
interrupt priority with which the channel is to run on next invocation. If the channel
is to be subsequently re-invoked, the user must ensure that the Channel Enable
Bit (R7.CEN) is set.
11.4.3.2 Error Condition Channel Exit
PCP error conditions can occur for a variety of reasons (e.g. an invalid operation code
was executed by a channel program, or an FPI Bus error occurred). When an error
condition occurs, the PCP Error Status Register (PCP_ES) is updated to reflect the error,
and the channel program is aborted. The error exit sequence is as follows:
• The channel enable bit R7.CEN is cleared. This means the channel program will be
unable to restart until another FPI Bus master has re-configured the channel
program’s stored context to set CR7.CEN to 1 again.
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