TC1796
System Units (Vol. 1 of 2)
On-Chip System Buses and Bus Bridges
User’s Manual 6-6 V2.0, 2007-07
Buses, V2.0
6.2.2.1 LMB Bus Default Master
When no LMB master is requesting the LMB, it is granted to the LMB default master. This
means if the default master needs the LMB in the next cycle, it can enter the address
cycle without running through a request/grant cycle.
6.2.3 LMB Bus Error Handling
When an error occurs on LMB, the LMB bus control unit captures and stores data about
the erroneous condition and generates a service request if enabled to do so. The
conditions that force an error-capture event are:
• Un-implemented address: No LMB slave responds to an address target
• Error acknowledge: An LMB slave responds with an error to a transaction
When a transaction causes an error, the address and data phase signals of the
transaction causing the error are captured and stored in the following registers:
• The LMB Error Address Register (LEADDR) stores the LMB address that has been
captured during the last erroneous LMB transaction.
• The LMB Error Data Low/High Registers (LEDATL/LEDTAH) store the 64-bit LMB
data bus information that has been captured during the last erroneous LMB
transaction.
• The LMB Error Attribute Register (LEATT) stores status information about the bus
error event.
If more than one LMB transaction generates a bus error, only the first bus error is
captured. After a bus error has been captured, the capture mechanism must be released
again by software.
If a transaction from the PCP, the DMA or the Cerberus causes a bus error on the DLMB,
the originating masters are not informed about this bus error because they are not a
DLMB master agent. With each bus error-capture event, a service request is generated
and an interrupt can be generated if enabled and configured in the corresponding service
request register.
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