Infineon Technologies TC1796 - 2.4.5 Memory Protection Registers

TC1796
System Units (Vol. 1 of 2)
CPU Subsystem
User’s Manual 2-20 V2.0, 2007-07
CPU, V2.0
2.4.5 Memory Protection Registers
As shown in Figure 2-10, there are two Memory Protection Register Sets in the TC1796,
Set 0 and Set 1, which specify memory protection ranges and permissions for code and
data. Set 2 and Set 3 are not implemented in the TC1796. The PSW.PRS bit field
determines which of these sets is currently in use by the CPU.
The Memory Protection Registers are described in detail in the TriCore 1 Architecture
Manual chapter - Memory Protection System.
Figure 2-10 Memory Protection Register Sets of the TC1796
Data Memory Protection Set 0
MCA05594
DPM0[31:24]DPR0_3UDPR0_3L
Range 3
DPM0[23:16]DPR0_2UDPR0_2L
Range 2
DPM0[15:8]DPR0_1UDPR0_1L
Range 1
DPM0[7:0]DPR0_0UDPR0_0L
Range 0
Code Memory Protection Set 0
CPM0[15:8]CPR0_1UCPR0_1L
Range 1
CPM0[7:0]CPR0_0UCPR0_0L
Range 0
Data Memory Protection Set 1
DPM1[31:24]DPR1_3UDPR1_3L
Range 3
DPM1[23:16]DPR1_2UDPR1_2L
Range 2
DPM1[15:8]DPR1_1UDPR1_1L
Range 1
DPM1[7:0]DPR1_0UDPR1_0L
Range 0
Code Memory Protection Set 1
CPM1[15:8]CPR1_1UCPR1_1L
Range 1
CPM1[7:0]CPR1_0UCPR1_0L
Range 0
Data and Code Memory
Protection Sets 0
are selected with
PSW.PRS = 00
B
Data and Code Memory
Protection Sets 1
are selected with
PSW.PRS = 01
B