TC1796
System Units (Vol. 1 of 2)
System Timer
User’s Manual 15-9 V2.0, 2007-07
STM, V2.0
15.3.1 General Module Register
The STM Clock Control Register is used to switch the STM on or off and to control its
input clock rate. After a power-on reset, the STM is always enabled and starts counting.
The STM can be disabled by setting bit DISR to 1.
STM_CLC
System Timer Clock Control Register (00
H
) Reset Value: 0000 0200
H
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
r
1514131211109876543210
0RMC0
FS
OE
SB
WE
E
DIS
SP
EN
DIS
S
DIS
R
r rw r rwwrwrw r rw
Field Bits Type Description
DISR 0rwModule Disable Request Bit
Used for enable/disable control of the STM module.
0
B
No disable requested
1
B
Disable requested
DISS 1rModule Disable Status Bit
Bit indicates the current status of the STM module.
0
B
STM module is enabled
1
B
STM module is disabled
SPEN 2rwModule Suspend Enable for OCDS
Used for enabling the suspend mode.
EDIS 3rwExternal Request Disable
Used for controlling the external clock disable
request.
SBWE 4wModule Suspend Bit Write Enable for OCDS
Determines whether SPEN and FSOE are write-
protected.
FSOE 5rwFast Switch Off Enable
Used for fast clock switch off in OCDS suspend mode.
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