TC1796
Peripheral Units (Vol. 2 of 2)
Micro Second Channel (MSC)
User’s Manual 21-21 V2.0, 2007-07
MSC, V2.0
21.1.3 Upstream Channel
The MSC upstream channel is an asynchronous serial receiver based on the standard
asynchronous data transfer protocol. It is dedicated to receive a serial data stream from
a peripheral device via its serial data input SDI, using two specific data frame formats.
Figure 21-14 is a block diagram of the MSC upstream channel.
Figure 21-14 Upstream Channel Block Diagram
The incoming data at SI is sampled after it has been filtered for spikes. The detected
logic states of the serial input are clocked into a shift register. After the complete
reception of the serial data frame, the content of the shift register is transferred into one
of the four data registers, and an interrupt can be generated optionally.
The receive baud rate is directly coupled to the module clock f
MSC
, and can be within a
range of f
MSC
/4 up to f
MSC
/256.
Upstream Data Registers
Serial Receive Buffer
Upstream
Channel
Control
RDI
SDI[7:0]
f
MSC
MCB05808
Samp-
ling
UD0
UD1
UD2
UD3
Shift Register
Spike
Filter
SI
Input Control
Interrupt
SDI
M
U
X
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