TC1796
System Units (Vol. 1 of 2)
Direct Memory Access Controller
User’s Manual 12-88 V2.0, 2007-07
DMA, V2.0
12.2.5 Channel Address Registers
The Source Address Register contains the 32-bit source address. If a DMA channel mx
is active, SADRmx is updated continuously (if programmed) and shows the actual
source address that is used for read moves within DMA transfers.
A write to SADRmx is executed directly only when the DMA channel mx is inactive
(CHSRmx.TCOUNT = 0 and TRSR.CHmx = 0). If DMA channel mx is active when
writing to SADRmx, the source address will not be written into SADRmx directly but will
be buffered in the shadow register SHADRmx until the start of the next DMA transaction.
During this shadowed address register operation, bit field ADRCRmx.SHCT must be set
to 01
B
.
DMA_SADR0x (x = 0-7)
DMA Channel 0x Source Address Register
(x*20
H
+90
H
) Reset Value: 0000 0000
H
DMA_SADR1x (x = 0-7)
DMA Channel 1x Source Address Register
(x*20
H
+190
H
) Reset Value: 0000 0000
H
31 0
SADR
rwh
Field Bits Type Description
SADR [31:0] rwh Source Start Address
This bit field holds the actual 32-bit source address of
DMA channel mx that is used for read moves.
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