TC1796
Peripheral Units (Vol. 2 of 2)
General Purpose Timer Array (GPTA)
User’s Manual 24-8 V2.0, 2007-07
GPTA, V2.0
24.2.2 Clock Generation Unit
As described in detail in the following sections, the Clock Generation Unit (CGU)
provides five signal pre-processing modules:
• Filter and Prescaler Cell (FPC)
• Phase Discrimination Logic (PDL)
• Duty Cycle Measurement Unit (DCM)
• Digital Phase Locked Loop Cell (PLL)
• Clock Distribution Module (CDU)
The Filter and Prescaler Cells (FPC) provide input noise filtering using a debounce
filter. FPCs are also able to operate as a prescaler for the GPTA module clock and
external signals. Each FPC can select among different data and clock input signals.
The Phase Discrimination Logic (PDL) is able to decode FPC debounce filtered and
phase encoded signals coming from a position and rotation direction sensor system. In
the PDL, phase encoding can be bypassed.
The Duty Cycle Measurement Units (DCM) provide signal measurement capabilities
(timer plus capture register, single and double capture on rising and falling edges or
both) as well as missing pulse detection/reconstruction functions.
The Digital Phase Locked Loop (PLL) is intended to generate a higher resolution clock
out of the values measured by DCM cells. Any arbitrary multiplication factor between 1
and 65535 is supported and may be changed from input clock period to input clock
period.
The Clock Distribution Unit (CDU) provides all Local and Global Timer Cells with a
variety of different clock signals. It is equipped with GPTA module clock prescalers and
multiplexers supporting alternate clock sources.
Figure 24-3 shows how the five modules of the CGU are interconnected. The external
interface signals of the CGU are:
• GPTA module clock f
GPTA
• GPTA module input signals (connected to the FPCs)
• Clock bus outputs (generated by the CDU)
• PDL bus outputs
• External PLL clock inputs (fed into CDU)
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