TC1796
System Units (Vol. 1 of 2)
System Control Unit
User’s Manual 5-50 V2.0, 2007-07
SCU, V2.0
5.9 Pad Test Mode Control
The pad test mode control logic in the SCU can be used for in-system tests of board
connections for dedicated pins (pins without GPIO functionality). The pad test mode can
be enabled in the normal operating mode of the TC1796. A special enable procedure
(two-word write sequence) avoids unintentionally enabling the pad test mode.
The pad test mode control logic especially makes it possible to:
• Output a value (low- or high-level) to dedicated pins
• Read the logic level on dedicated pins
Figure 5-12 shows the pad test mode control logic for one pad/pin. Test data is read or
written via four pad test data registers. These registers with numbering index n (n = 0-3)
make it possible to access at maximum sixteen of the dedicated pins, independently
from each other.
Figure 5-12 Pad Test Mode Control in the SCU
When the pad test mode is disabled (PTMEN = 0), the dedicated pads are in their normal
operating mode. The pad output drivers are controlled by the hardware part that
determines whether the dedicated pad/pin is used for input, output, or for I/O purposes.
When the pad test mode is enabled, PTMEM is set. A value written into register PTDATn
is always output at the corresponding pad as inverted state. This means when writing a
1 (0) to a bit of register PTDATn, a low (high) level will be available at the corresponding
dedicated pin. When reading register PTDATn, either the (non-inverted) logic level at the
dedicated pad (RDSSn = 0) or the value of the PTDATn register bit (RDSSn = 1) can be
M
U
X
MCA05623
Control
1 Bit in
Register
PTDATn
FPI Bus
Pad
Logic for
Regular
Operation
of
I/O Pad
PTMEN
PTMLC
ENOUTn
M
U
X
Write
PTDATn
Read
PTDATn
RDSSn
SCU
Pad Driver
M
U
X
0
1
0
1
0
1
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