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TC1796

System Units (Vol. 1 of 2)

CPU Subsystem

User’s Manual 2-15 V2.0, 2007-07

CPU, V2.0

2.4.3 CPU General Purpose Registers

Figure 2-8 GPR Registers

Table 2-4 GPR Registers

Name

D0 Data Register 0 F7E1 FF00

D1 Data Register 1 F7E1 FF04

D2 Data Register 2 F7E1 FF08

D3 Data Register 3 F7E1 FF0C

D4 Data Register 4 F7E1 FF10

D5 Data Register 5 F7E1 FF14

D6 Data Register 6 F7E1 FF18

D7 Data Register 7 F7E1 FF1C

D8 Data Register 8 F7E1 FF20

D9 Data Register 9 F7E1 FF24

D10 Data Register 10 F7E1 FF28

MCA05592

A15 (implicit address) D15 (implicit data)

Address General

Purpose Registers

(AGPR)

Data General

Purpose

Registers (DGPR)

A14 D14

D13

D12

D11

D10

E14

E12

E10

64-Bit Extended

Data Registers

A13

A12

A11 (return address)

A10 (stack pointer)

A9 (global address)

A8 (global address)

A1 (global address)

A0 (global address)

Table of Contents9
- System Units (Vol. 1 of 2)9
- Peripheral Units (Vol. 2 of 2)28
1 Introduction40
- 1.1 About this Document40
- 1.2 System Architecture of the TC179647
  - 1.2.1 TC1796 Block Diagram48
  - 1.2.2 Features49
- 1.3 On-Chip Peripheral Units of the TC179653
- 1.4 TC1796 Pin Definitions and Functions73
2 CPU Subsystem98
- 2.1 TC1796 Processor Subsystem98
- 2.2 Central Processing Unit Features99
- 2.3 Implementation-specific Features104
- 2.4 TC1796 CPU Subsystem Registers106
- 2.5 Program Memory Interface (PMI)121
- 2.6 Data Memory Interface (DMI)128
- 2.7 Instruction Timing137
  - 2.7.1 Integer-Pipeline Instructions138
  - 2.7.2 Load-Store Pipeline Instructions145
- 2.8 Floating Point Pipeline Timings149
3 Clock System and Control150
- 3.1 Overview150
- 3.2 Clock Generation Unit152
- 3.3 Module Power Management and Clock Gating171
- 3.4 System Clock Output Control190
  - 3.4.1 System Clock Fractional Divider Register191
4 Reset and Boot Operation193
- 4.1 Reset and Boot Overview193
  - 4.1.1 Reset Status and Control Registers195
    - 4.1.1.1 Reset Status Register195
    - 4.1.1.2 Reset Request Register197
- 4.2 Reset Operations199
- 4.3 Boot ROM208
- 4.4 Bootstrap Loader (BSL)212
5 System Control Unit223
- 5.1 Power Management224
- 5.2 Configuration Input Sampling230
- 5.3 External Request Unit (ERU)231
- 5.4 Special System Interrupts257
- 5.5 SRAM Parity Control259
  - 5.5.1 Parity Error Trap Registers261
- 5.6 Pad Driver Temperature Compensation Control263
  - 5.6.1 Functional Description263
  - 5.6.2 Temperature Compensation Registers266
- 5.7 Die Temperature Sensor270
- 5.8 GPTA1 Input IN1 Control271
- 5.9 Pad Test Mode Control272
  - 5.9.1 Pad Test Mode Enabling273
  - 5.9.2 Pad Test Mode Registers273
- 5.10 Emergency Stop Output Control for GPTA and MSC279
- 5.11 Analog Input 7 Testmode282
- 5.12 SCU Registers and Address Map283
- 5.13 Miscellaneous SCU Registers286
6 On-Chip System Buses and Bus Bridges294
- 6.1 Program and Data Local Memory Buses295
- 6.2 Local Memory Bus Controller Units298
- 6.3 Local Memory to FPI Bus Interface (LFI Bridge)308
  - 6.3.1 Functional Overview308
  - 6.3.2 LFI Register309
- 6.4 System and Remote Peripheral Bus312
- 6.5 FPI Bus Control Units (SBCU and RBCU)317
7 Program Memory Unit352
- 7.1 Boot ROM352
- 7.2 Program & Data Flash Memory353
- 7.3 Emulation Interface412
8 Data Memory Unit413
- 8.1 DLMB/PLMB Interfaces414
- 8.2 SBRAM414
- 8.3 SRAM414
- 8.4 Parity Protection for DMU Memories415
- 8.5 Data Access Overlay Functionality415
- 8.6 Program Local Memory Bus Interface (LMI)420
  - 8.6.1 Data Read Buffer420
- 8.7 DMU Registers422
9 Memory Maps431
- 9.1 How to Read the Address Maps431
- 9.2 Contents of the Segments434
- 9.3 Address Map of the FPI Bus System436
  - 9.3.1 Segments 0 to 14436
  - 9.3.2 Segment 15440
- 9.4 Address Map of the Program Local Memory Bus (PLMB)445
- 9.5 Address Map of the Data Local Memory Bus (DLMB)449
- 9.6 Memory Module Access Restrictions452
10 General Purpose I/O Ports and Peripheral I/O Lines453
- 10.1 Basic Port Operation454
- 10.2 Port Register Description457
- 10.3 Port 0470
- 10.4 Port 1478
- 10.5 Port 2484
- 10.6 Port 3492
- 10.7 Port 4499
- 10.8 Port 5506
- 10.9 Port 6511
- 10.10 Port 7517
- 10.11 Port 8522
- 10.12 Port 9527
- 10.13 Port 10 (Hardware Select Inputs)533
  - 10.13.1 Port 10 Configuration533
  - 10.13.2 Port 10 Registers534
    - 10.13.2.1 Port 10 Input Register534
- 10.14 Dedicated Peripheral I/O Lines535
  - 10.14.1 Dedicated I/O Lines for SSC0 and SSC1535
  - 10.14.2 LVDS Outputs of MSC0 and MSC1537
11 Peripheral Control Processor (PCP)538
- 11.1 Peripheral Control Processor Overview538
- 11.2 PCP Architecture539
- 11.3 PCP Programming Model543
- 11.4 PCP Operation565
- 11.5 PCP Interrupt Operation569
- 11.6 PCP Error Handling575
- 11.7 Instruction Set Overview577
- 11.8 Accessing PCP Resources from the FPI Bus585
- 11.9 Debugging the PCP587
- 11.10 PCP Registers589
- 11.11 PCP Instruction Set Details609
- 11.12 Programming of the PCP649
- 11.13 PCP Programming Notes and Tips655
- 11.14 Implementation of the PCP in the TC1796662
12 Direct Memory Access Controller665
- 12.1 DMA Controller Kernel Description666
- 12.2 DMA Module Kernel Registers706
- 12.3 DMA Module Implementation755
- 12.4 Memory Checker Module774
  - 12.4.1 Functional Description774
  - 12.4.2 Registers775
    - 12.4.2.1 Memory Checker Registers776
13 LMB External Bus Unit779
- 13.1 Block Diagram780
- 13.2 EBU Interface Signals781
- 13.3 External Bus Arbitration785
- 13.4 Start-Up/Boot Process798
- 13.5 Master Mode Operation803
- 13.6 PLMB Data Buffering817
- 13.7 Standard Access Phases819
- 13.8 Asynchronous Read/Write Accesses828
- 13.9 Burst Mode Read Accesses843
- 13.10 EBU Registers857
14 Interrupt System890
- 14.1 Overview890
- 14.2 Service Request Nodes892
  - 14.2.1 Service Request Control Registers892
- 14.3 Interrupt Control Units897
  - 14.3.1 Interrupt Control Unit (ICU)897
    - 14.3.1.1 ICU Interrupt Control Register (ICR)897
    - 14.3.1.2 Operation of the Interrupt Control Unit (ICU)899
  - 14.3.2 PCP Interrupt Control Unit (PICU)900
- 14.4 Arbitration Process901
  - 14.4.1 Controlling the Number of Arbitration Cycles901
  - 14.4.2 Controlling the Duration of Arbitration Cycles902
- 14.5 Entering an Interrupt Service Routine902
- 14.6 Exiting an Interrupt Service Routine903
- 14.7 Interrupt Vector Table904
- 14.8 Usage of the TC1796 Interrupt System907
- 14.9 Service Request Node Table912
- 14.10 Non-Maskable Interrupt914
15 System Timer918
- 15.1 Overview918
- 15.2 Operation918
- 15.3 Kernel Registers924
16 Watchdog Timer939
- 16.1 Watchdog Timer Overview939
- 16.2 Features of the Watchdog Timer940
- 16.3 The Endinit Function941
- 16.4 Watchdog Timer Operation943
- 16.5 Handling the Watchdog Timer960
- 16.6 Watchdog Timer Registers966
17 On-Chip Debug Support973
- 17.1 Overview973
- 17.2 OCDS Level 1976
- 17.3 OCDS Level 2 Debugging via Trace Port982
- 17.4 Debug Interface (Cerberus)984
- 17.5 JTAG Interface987
- 17.6 Cerberus and JTAG Registers988
18 Register Overview990
- 18.1 Address Map of Segment 15991
- 18.2 Registers Tables996
19 Asynchronous/Synchronous Serial Interface (ASC)1116
- 19.1 ASC Kernel Description1116
- 19.2 ASC Kernel Registers1134
- 19.3 ASC0/ASC1 Module Implementation1145
20 Synchronous Serial Interface (SSC)1158
- 20.1 SSC Kernel Description1158
  - 20.1.1 Overview1159
  - 20.1.2 General Operation1160
- 20.2 SSC Kernel Registers1184
- 20.3 SSC0/SSC1 Module Implementation1203
21 Micro Second Channel (MSC)1218
- 21.1 MSC Kernel Description1220
- 21.2 MSC Kernel Registers1253
- 21.3 MSC Module Implementation1279
22 Controller Area Network (MultiCAN) Controller1296
- 22.1 CAN Basics1297
- 22.2 Overview1309
  - 22.2.1 MultiCAN Module1310
  - 22.2.2 Time-Triggered Extension (TTCAN)1312
- 22.3 MultiCAN Kernel Functional Description1313
- 22.4 MultiCAN Kernel Registers1353
- 22.5 Time-Triggered Extension (TTCAN Controller)1409
- 22.6 TTCAN Scheduler1418
- 22.7 TTCAN Operation1443
- 22.8 TTCAN Registers1449
- 22.9 MultiCAN Module Implementation1494
23 Micro Link Interface (MLI)1510
- 23.1 Functional Description1511
- 23.2 Module Kernel Description1534
- 23.3 Operating the MLI1576
- 23.4 MLI Kernel Registers1584
- 23.5 Implementation of the MLI0/MLI1 in TC17961633
24 General Purpose Timer Array (GPTA)1656
- 24.1 GPTA Overview1657
  - 24.1.1 Functionality of GPTA0 and GPTA11658
  - 24.1.2 Functionality of LTCA21660
- 24.2 GPTA0/GPTA1 Kernel Description1661
- 24.3 GPTA0/1 Kernel Registers1805
- 24.4 LTCA2 Kernel Description1872
- 24.5 LTCA2 Kernel Registers1888
- 24.6 GPTA Module Implementation1902
25 Analog-to-Digital Converter (ADC)1932
- 25.1 ADC Kernel Description1932
- 25.2 ADC0/ADC1 Kernel Registers1988
- 25.3 Implementation of ADC0/ADC12031
26 Fast Analog-to-Digital Converter (FADC)2052
- 26.1 FADC Kernel Description2053
- 26.2 FADC Kernel Registers2078
- 26.3 Implementation of FADC2107
Keyword Index2117
Register Index2132

Brand	Infineon Technologies
Model	TC1796
Category	Controller
Language	English

Infineon Technologies TC1796 User Manual

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Infineon Technologies TC1796 Specifications