TC1796
System Units (Vol. 1 of 2)
Peripheral Control Processor (PCP)
User’s Manual 11-1 V2.0, 2007-07
PCP, V2.0
11 Peripheral Control Processor (PCP)
This chapter describes the Peripheral Control Processor (PCP), its architecture,
programming model, registers, and instructions. The TC1796’s PCP is an enhanced
version 2 (PCP2) of the TC1775’s PCP peripheral control processor.
Section 11.1 to Section 11.13 of this chapter describe the TC1796 PCP in general.
TC1796 implementation-specific details are described in Section 11.14.
11.1 Peripheral Control Processor Overview
The PCP in the TC1796 performs tasks that would normally be performed by the
combination of a DMA controller and its supporting CPU interrupt service routines in a
traditional computer system. It could easily be considered as the host processor’s first
line of defence as an interrupt-handling engine. The PCP can unload the CPU from
having to service time-critical interrupts. This provides many benefits, including:
• Avoiding large interrupt-driven task context-switching latencies in the host processor
• Reducing the cost of interrupts in terms of processor register and memory overhead
• Improving the responsiveness of interrupt service routines to data-capture and data-
transfer operations
• Easing the implementation of multitasking operating systems.
The PCP has an architecture that efficiently supports DMA-type transactions to and from
arbitrary devices and memory addresses within the TC1796 and also has reasonable
stand-alone computational capabilities.
The TC1796 contains an improved version of the TC1775’s PCP with the following
enhancements:
• Optimized context switching
• Support for nested interrupts
• Enhanced instruction set
• Enhanced instruction execution speed
• Enhanced interrupt queueing
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