Infineon Technologies TC1796 User Manual

TC1796
System Units (Vol. 1 of 2)
Memory Maps
User’s Manual 9-10 V2.0, 2007-07
MemMaps, V2.0
9.3.2 Segment 15
Table 9-3 shows the address map of segment 15 as seen from the SPB and RPB bus
masters PCP, DMA, and OCDS. Please note that access in Table 9-3 means only that
an access to an address within the defined address range is not automatically incorrect
or ignored. If an access is really addressing a correct address, it can be found in the
detailed tables in Chapter 18.
Table 9-3 SPB/RPB Address Map of Segment 15
Unit Unit Unit Access Type
Read Write
System Control Unit (SCU) and
Watchdog Timer (WDT)
F000 0000
H
-
F000 00FF
H
256 byte access access
System Peripheral Bus Control Unit
(SBCU)
F000 0100
H
-
F000 01FF
H
256 byte access access
System Timer (STM) F000 0200
H
-
F000 02FF
H
256 byte access access
Reserved F000 0300
H
-
F000 03FF
H
– SPBBE SPBBE
On-Chip Debug Support (Cerberus) F000 0400
H
-
F000 04FF
H
256 byte access access
Reserved F000 0500
H
-
F000 07FF
H
– SPBBE SPBBE
MicroSecond Bus Controller 0
(MSC0)
F000 0800
H
-
F000 08FF
H
256 byte access access
MicroSecond Bus Controller 1
(MSC1)
F000 0900
H
-
F000 09FF
H
256 byte access access
Async./Sync. Serial Interface 0
(ASC0)
F000 0A00
H
-
F000 0AFF
H
256 byte access access
Async./Sync. Serial Interface 1
(ASC1)
F000 0B00
H
-
F000 0BFF
H
256 byte access access
Port 0 F000 0C00
H
-
F000 0CFF
H
256 byte access access
Port 1 F000 0D00
H
-
F000 0DFF
H
256 byte access access
Port 2 F000 0E00
H
-
F000 0EFF
H
256 byte access access

Infineon Technologies TC1796 Specifications

General

Brand	Infineon Technologies
Model	TC1796
Category	Controller
Language	English