TC1796
System Units (Vol. 1 of 2)
Direct Memory Access Controller
User’s Manual 12-103 V2.0, 2007-07
DMA, V2.0
12.3.3 Implementation-specific DMA Registers
The DMA controller as implemented in the TC1796 contains the following additional
registers:
• DMA clock control register
• Service request control registers for DMA controller interrupts (DMA_SRCx)
• Service request control registers for MLI module interrupts (DMA_MLIySRC.x)
• Service request control registers for system related interrupts (DMA_SYSSRCx)
Figure 12-32 is an overview of these registers.
Figure 12-31 DMA Implementation-specific Registers
Note: Further details on interrupt handling and processing are described in the “Interrupt
System” chapter of the TC1796 System Units User’s Manual.
The clock generation and interrupt control configuration as implemented in the DMA
controller module is shown in Figure 12-32.
The DMA controller and the two MLI modules (MLI0 and MLI1) are supplied from a
common module clock f
DMA
that has the frequency of the system clock fSYS and is
controlled via the DMA_CLC clock control register. The MLI modules do not have their
own clock control registers. Their input clock is derived from the DMA clock divided by
separate fractional divider registers.
The control of the suspend and break features is done independently inside each
module, except for the hard-suspend feature of the DMA (clock switch-off). This hard-
suspend feature should only be used if the system is reset after the suspend state is left.
In Hard-suspend Mode, the FPI Bus interface 1 (RPB) can not be accessed, because
the DMA Bus Switch is no longer clocked.
The DMA controller contains in total 18 interrupt request nodes with its interrupt service
request control registers:
DMA Interrupt
Registers
Control Register
DMA_CLC DMA_SRC0
DMA_SRC1
DMA_SRC2
DMA_SRC3
DMA_SRC4
DMA_SRC5
DMA_SRC6
DMA_SRC7
MCA05708
MLI Interrupt
Registers
DMA_MLI0SRC0
DMA_MLI0SRC1
DMA_MLI0SRC2
DMA_MLI0SRC3
DMA_MLI1SRC0
DMA_MLI1SRC1
System Interrupt
Registers
DMA_SYSSRC0
DMA_SYSSRC1
DMA_SYSSRC2
DMA_SYSSRC3
DMA_SYSSRC4
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