Infineon Technologies TC1796 - 24.6.3.3 Pad Driver Characteristics Selection

TC1796
Peripheral Units (Vol. 2 of 2)
General Purpose Timer Array (GPTA)
User’s Manual 24-253 V2.0, 2007-07
GPTA, V2.0
24.6.3.3 Pad Driver Characteristics Selection
The output driver strength and the slew rate of GPTA output lines is controlled by 3-bit
wide PDX bit fields located in the pad driver mode registers PDR. These bit fields
determine the driver strength and the slew rate for a group of port output lines.
Table 24-26 shows which of the pad driver register bit field is related to a specific
GPTA0/GPTA1/LTCA2 module I/O line group.
PDx Selection Table
Table 24-26 PDR Assignment for GPTA Port Lines
Port Pad
Class
PDR Register
PDx Bit Field
Controlled Port Lines Related GPTA
Output Lines
Port 2 A1 P2_PDR.PD1 P2.[15:8] OUT[7:0]
Port 3 A1 P3_PDR.PD0 P3.[7:0] OUT[15:8]
P3_PDR.PD1 P3.[15:8] OUT[23:16]
Port 4 A2 P4_PDR.PD0 P4.[7:0] OUT[31:24]
A1 P4_PDR.PD1 P4.[15:8] OUT[39:32]
Port 8 A1 P8_PDR.PD0 P8.1, P8.4, P8.6, P8.7 OUT41, OUT44,
OUT46, OUT47
A2 P8_PDR.MLI1 P8.0, P8.2, P8.3, P8.5 OUT40, OUT42,
OUT43, OUT45
Port 9 A2 P9_PDR.PDMSC0 P9.[7:4] OUT[55:52]
P9_PDR.PDMSC1 P9.[3:0] OUT[51:48]
Table 24-27 Pad Driver Mode Mode Selection (Class A1/A2 Pads)
Pad Class PDx Bit Field Driver Strength Signal Transitions
A1 XX0
B
Medium driver –
XX1
B
Weak driver –