TC1796
System Units (Vol. 1 of 2)
Direct Memory Access Controller
User’s Manual 12-106 V2.0, 2007-07
DMA, V2.0
12.3.3.2 DMA Service Request Control Registers
In the TC1796, only the lower eight DMA controller interrupts SR[7:0] are connected to
service request control registers. The upper eight DMA controller interrupt outputs
SR[15:8] are not used and not connected.
DMA_SRCx (x = 0-7)
DMA Service Request Control Register x
(2FC
H
-x*4
H
) Reset Value: 0000 0000
H
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
r
1514131211109876543210
SET
R
CLR
R
SRR SRE 0 TOS 0 SRPN
w w rh rw r rw r rw
Field Bits Type Description
SRPN [7:0] rw Service Request Priority Number
TOS 10 rw Type of Service Control
SRE 12 rw Service Request Enable
SRR 13 rh Service Request Flag
CLRR 14 w Request Clear Bit
SETR 15 w Request Set Bit
0 [9:8], 11,
[31:16]
r Reserved
Read as 0; should be written with 0.
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