TC1796
System Units (Vol. 1 of 2)
Direct Memory Access Controller
User’s Manual 12-10 V2.0, 2007-07
DMA, V2.0
12.1.4.2 DMA Channel Request Control
Figure 12-6 shows the control logic for DMA requests that is implemented for each DMA
channel.
Figure 12-6 Channel Request Control
Two different types of DMA requests are possible:
• Hardware DMA requests
• Software DMA requests
The hardware request CHmn_REQ can be connected to one of eight possible hardware
request input lines as selected by bit field CHCRmn.PRSEL. Hardware requests are
enabled/disabled by status bit TRSR.HTREmn. HTREmn can be set/cleared by software
or by hardware in Single Mode at the end of a DMA transaction. A software request can
be generated by setting bit STREQ.SCH0n.
Status flag TRSR.CHmn indicates whether or not a software or hardware generated
DMA request for DMA channel mn is pending. TRSR.CHmn can be cleared by software
or by hardware at the end of a DMA transfer (RROAT = 0) or at the end of a DMA
transaction (RROAT = 1).
M
U
X
MCA05685c
TRSR
Transfer
Request
To
Channel
Arbiter
HTREmn
3
CHCRmn
PRSEL
CHmn_REQ
STREQ
SCHmn
&
TRSR
CHmn
Set
Clear
CHCRmn
RROAT
End of
Transfer
Clear
Set
Clear
M
U
X
CHCRmn
CHMODE
Suspend Control
&
SUSENmn
SUSPMR
TRSR
0
1
End of
Transaction
DCHmn
ECHmn
HTREQ
Suspend Request
&
Transfer
Request
Lost
Interrupt
ERRSR
TRLmn
&
Set
CHRSTR
CHmn
CHmn_REQI0
CHmn_REQI1
CHmn_REQI2
CHmn_REQI3
CHmn_REQI4
CHmn_REQI5
CHmn_REQI6
CHmn_REQI7
End of
Transaction
≥1
≥1
Pattern
Match
Clear
Clear
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