Infineon Technologies TC1796 User Manual

TC1796
Peripheral Units (Vol. 2 of 2)
Fast Analog-to-Digital Converter (FADC)
User’s Manual 26-5 V2.0, 2007-07
FADC, V2.0
26.1.1.1 Analog Input Stage Configurations
The analog input stage makes it possible to select different configurations to be selected
independently for each FADC channel x. These combinations are shown in Figure 26-3.
Figure 26-3 Analog Input Stage Configurations
Configuration 0 (ACRx.ENP = ACRx.ENN = 0)
FADC channel x inputs FAINxP and FAINxN are in a high impedance state and the
channel amplifier of the analog input stage is in power-down mode.
Configuration 1 (ACRx.ENP = 0 and ACRx.ENN = 1)
This configuration enables the single-ended measurement mode for V
VAREF
/2 - FAINxN:
The positive analog input FAINxP is disconnected is in a high impedance state. The
negative analog input FAINxN is connected to the channel amplifier (input impedance is
determined by Rn). The positive input of the channel amplifier is connected to V
FAREF
/2
(1.65 V with V
FAREF
= 3.3 V). If the voltage at the negative input FAINxN varies, the
FADC will deliver conversion results as follows (gain = 1 selected by ACRx.GAIN = 00
B
):
MCA06040
V
FAREF
/2
Rn
Configuration 1:
Single-ended Measurement
of V
FAREF
/2 - FAINxN
Rp
Rp
Rn
Configuration 2:
Single-ended Measurement
of FAINxP - V
FAREF
/2
Configuration 3:
Differential Measurement of
FAINxP - FAINxN
Configuration 0:
Channel amplifier is in
Power Down Mode
N.C.
High
impedance
High
impedance
High
impedance
V
FAREF
/2
High
impedance
-
+
-
+
-
+
-
+
FAINxN
FAINxP
FAINxP
FAINxN
FAINxN
FAINxP
FAINxP
FAINxN

Infineon Technologies TC1796 Specifications

General

Brand	Infineon Technologies
Model	TC1796
Category	Controller
Language	English