TC1796
System Units (Vol. 1 of 2)
CPU Subsystem
User’s Manual 2-23 V2.0, 2007-07
CPU, V2.0
2.4.5.1 Implementation-specific Memory Protection Registers
This section describes the implementation-specific Code Protection Mode Registers that
differ from the description in the TriCore 1 Architecture Manual. The non-shaded areas
in the CPMx register descriptions define the implementation-specific bits/bit fields.
Therefore, the uppermost 16 bits of CPMx are of type “0, r”.
CPMx (x = 0, 1)
Code Protection Mode Register Set x Reset Value: 0000 0000
H
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
r
1514131211109876543210
XE
1
0
XS
1
0
BL
1
0 0
BU
1
XE
0
0
XS
0
0
BL
0
0 0
BU
0
rw rr rw rr rw rr rr rw rw rr rw r rw rr rr rw
Field Bits Type Description
0 [31:16] r Reserved
Read as 0; should be written with 0.
These bits refer to code memory ranges 2 and 3, which are
are not available in the TC1796.
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