Infineon Technologies TC1796 - Page 119

TC1796
System Units (Vol. 1 of 2)
CPU Subsystem
User’s Manual 2-22 V2.0, 2007-07
CPU, V2.0
CPR0_0L Code Segment Protection Register Set 0, Range 0,
Lower Boundary
F7E1 D000
H
CPR0_0U Code Segment Protection Register Set 0, Range 0,
Upper Boundary
F7E1 D004
H
CPR0_1L Code Segment Protection Register Set 0, Range 1,
Lower Boundary
F7E1 D008
H
CPR0_1U Code Segment Protection Register Set 0, Range 1,
Upper Boundary
F7E1 D00C
H
CPR1_0L Code Segment Protection Register Set 1, Range 0,
Lower Boundary
F7E1 D400
H
CPR1_0U Code Segment Protection Register Set 1, Range 0,
Upper Boundary
F7E1 D404
H
CPR1_1L Code Segment Protection Register Set 1, Range 1,
Lower Boundary
F7E1 D408
H
CPR1_1U Code Segment Protection Register Set 1, Range 1,
Upper Boundary
F7E1 D40C
H
DPM0 Data Protection Mode Register Set 0 F7E1 E000
H
DPM1 Data Protection Mode Register Set 1 F7E1 E080
H
CPM0 Code Protection Mode Register Set 0 F7E1 E200
H
CPM1 Code Protection Mode Register Set 1 F7E1 E280
H
Table 2-6 Memory Protection Registers (cont’d)
Register
Short Name
Register Long Name Address