TC1796
Peripheral Units (Vol. 2 of 2)
Analog-to-Digital Converter (ADC)
User’s Manual 25-51 V2.0, 2007-07
ADC, V2.0
25.1.10.2 Status Information During Synchronized Conversion
Each ADC module provides three status bits in register STAT that display the status of
the ADC module during a Synchronized Injection.
• Master Status:
Bit STAT.REQSY is set in the initiating (master) ADC module during a synchronized
conversion. It is set at the start of the synchronized conversion and is cleared after
this synchronized conversion is finished.
• Slave Status:
Bit STAT.PARSY is set in the slave ADC module during a synchronized conversion.
It is set at the start of the synchronized conversion and is cleared after this
synchronized conversion is finished.
• Master/Slave Status:
Bit STAT.SYMS is set in both ADC modules, to indicate that both ADC modules
requested a synchronized conversion at the same time with identical channel
number. Bit STAT.SYMS is automatically cleared at the generation of the
synchronized service request.
25.1.10.3 Master-Slave Functionality for Synchronized Injection
Each ADC module can operate either as master or slave or both. The ADC module
operating functionality for Synchronized Injection (master, slave or master/slave
functionality) is automatically detected. All associated controls for synchronized
conversion are shown in Table 25-11.
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