TC1796
System Units (Vol. 1 of 2)
Direct Memory Access Controller
User’s Manual 12-24 V2.0, 2007-07
DMA, V2.0
after Suspend Mode has been left again. Suspend Mode of DMA channel mn is left and
its normal operation continues if either the SUSREQ signal becomes inactive, or if the
enable bit SUSENmn is cleared by software.
Figure 12-15 Soft-suspend Mode Control
12.1.7.3 Break Signal Generation
The DMA controller provides one BREAK output signal that is generated for the on-chip
debug support logic (see Figure 12-16). Each of the DMA Sub-Blocks is able to detect
two break conditions:
• Transaction lost interrupt has occurred
• DMA request transitions, indicated by bits TRSR.CHmn
The output lines of the two break conditions in each DMA Sub-Block are OR-ed together
to the BREAK output signal.
A transaction lost break condition occurs in DMA Sub-Block m whenever at least one of
its eight transaction lost interrupts becomes active, and when enable bit OCDSR.BRLm
is set. The transaction lost interrupts do not generate a break condition if
OCDSR.BRLm = 0. Transaction interrupt control is described in Section 12.1.8.2.
The second break condition of DMA Sub-Block m becomes active when the transaction
request bit TRSR.CHmn of one of its eight DMA channels n (as selected by
OCDSR.BCHSn) indicates a transition of its state. The CHmn transition type (set,
cleared, or set and cleared) is selected by bit field OCDSR.BTCRn.
MCA05694
Soft Suspend
Control
Transfer
Request to
Channel
Arbiter
TRSR
CHmn
&
SUSREQ
SUSACmn
SUSPMR
Set
SUSENmn
SUSPMR
Transaction
Control Unit m
(Move Engine m)
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