TC1796
System Units (Vol. 1 of 2)
Data Memory Unit
User’s Manual 8-2 V2.0, 2007-07
DMU, V2.0
8.1 DLMB/PLMB Interfaces
The DLMB interface is used for execution of data read write operations to/from the DMU
memories and registers.
The PLMB interface is used when data accesses from internal or external code memory
are redirected to data read accesses from the SRAM memory (data access overlay
capability for calibration purposes).
8.2 SBRAM
The 16 Kbyte SBRAM provides stand-by functionality. It is connected to a separate
power supply pin V
DDSBRAM
. This power supply pin provides the power for normal
operation of SBRAM, and during power-off state of the TC1796. If V
DDSBRAM
does not
drop below a specified voltage level in power-down mode (specified in Data Sheet), the
SBRAM will remain its memory content. The switch between regular supply voltage and
power-down mode supply voltage must be done externally.
In order to maintain the memory contents when switching into power-down mode and
coming back from power-down mode, the SBRAM must be locked. This SBRAM lock
mechanism is controlled by the Stand-by SRAM Control Register SBRCTR. When
writing a dedicated pattern into bit fields STBULK and STBSLK, the SBRAM will be
locked. A status flag STBLOCK indicates whether the SBRAM is locked or not. To unlock
the SBRAM, register SBRCTR must be written by three consecutive write operations (for
a detailed description see Page 8-12.
).
If an access to the SBRAM is performed while the SBRAM is locked, an error
acknowledge will be issued as response to the access.
8.3 SRAM
64 Kbyte of fast SRAM are available in the DMU. Besides being used for normal data
storage, this memory can be used to shadow the active portions of the Data Flash and
as overlay RAM for calibration/instrumentation support.
The SRAM can operate as fast mirror memory during Data Flash EEPROM emulation.
In this application, a copy of the active DFLASH region (typically 16 Kbyte) is stored in
the SRAM memory and can be accessed (read/written) very fast. More details about
Data Flash EEPROM emulation are described on Page 7-26.
The SRAM also provides an overlay functionality. During calibration operations, SRAM
memory can be the target of redirected data accesses from internal or external code
memories. The redirection process is described in the following section.
To Next Page
Loading...
Need help?
General