TC1796
System Units (Vol. 1 of 2)
Data Memory Unit
User’s Manual 8-12 V2.0, 2007-07
DMU, V2.0
The Stand-by SRAM Control Register SBRCTR controls the locking and unlocking of the
DMU stand-by memory (SBRAM).
SBRCTR
Stand-by SRAM Control Register (E0
H
) Reset Value: 0000 0000
H
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
r
1514131211109876543210
0 STBSLK STBULK
STB
LOC
K
rwwrh
Field Bits Type Description
STBLOCK 0rhStand-by Lock Flag
Shows the current lock state of the SBRAM.
0
B
SBRAM is locked
1
B
SBRAM is unlocked
STBULK [3:1] w Unlock Stand-by Lock Flag
In order to unlock the SBRAM, three consecutive write
cycles must be written into STBULK with the following
pattern:
1. Write STBULK = 001
B
2. Write STBULK = 011
B
3. Write STBULK = 111
B
During the three consecutive write operations, STBSLK
must be written with 0000
B
. If any bit of STBSLK is set
when writing a non-zero pattern to STBULK, this is
treated as invalid pattern and the SBRAM will not be
unlocked. Reading STBULK always return 000
B
.
STBSLK [7:4] w Set Stand-by Lock Flag
In order to lock the SBRAM, the value 1001
B
must be
written into STBSLK. At the same time, the value 000
B
must be written into STBULK. If any bit of STBULK is
set when writing 1001
B
to STBSLK, this is treated as
invalid pattern and the SBRAM will not be locked.
Reading STBSLK always returns 0000
B
.
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