TC1796
System Units (Vol. 1 of 2)
On-Chip Debug Support
User’s Manual 17-10 V2.0, 2007-07
OCDS, V2.0
17.3 OCDS Level 2 Debugging via Trace Port
The OCDS Level 2 debug support extends the OCDS Level 1 debug functionalities with
an additional 16-bit wide trace port TR[15:0] with the trace clock TRCLK. The trace port
extension makes it possible to output one out of four types of trace output signals:
• TriCore CPU OCDS Level 2 trace
• PCP OCDS Level 2 trace
• DMA Controller channel transaction request trace
• DMA Controller move engine trace
The trace output port is controlled by the OSCU. The trace data is always output at CPU
clock speed (
f
TRCLK
= f
CPU
).
17.3.1 TriCore CPU and PCP OCDS Level 2 Trace
Every trace clock cycle, 16 bits of CPU/PCP trace information are sent out, representing
the current state of the CPU/PCP cores. The trace output lines are grouped into three
parts:
• 5 bits of pipeline status information
• 8-bit indirect PC bus information
• 3 bits of breakpoint qualification information
With this information, an external emulator can reconstruct a cycle-by-cycle image of the
instruction flow through the CPU or PCP. The trace information can be captured by the
external debugger hardware and used to rebuild later on (off-line, using the source code)
a cycle accurate disassembly of the code that has been executed. It’s also possible to
follow in real-time the current PC, facilitating advanced tools such as profilers, coverage
analysis tools etc.
17.3.2 DMA OCDS Level 2 Trace
The DMA controller provides two sources for OCDS Level 2 tracing:
• DMA Controller channel transaction request trace
• DMA Controller move engine trace
More details on the OCDS Level 2 debug trace capabilities of the DMA controller are
described in detail in section “Trace Signal Generation” on Page 12-25.
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