TC1796
Peripheral Units (Vol. 2 of 2)
Fast Analog-to-Digital Converter (FADC)
User’s Manual 26-61 V2.0, 2007-07
FADC, V2.0
Note: Additional details on the fractional divider register functionality are described in
section “Fractional Divider Operation” on Page 3-29 of the TC1796 User’s
Manual System Units part (Volume 1).
26.3.4 Port Control
The external request inputs REQ0, REQ1, REQ4, and REQ5 used by the FADC module
are controlled in the port logic. If these input lines are used as FADC input, the input
function selection (IOCR registers) must be checked.
Input Function Selection
The port input/output control registers contain the bit fields that select the FADC’s digital
input driver characteristics such as pull-up/pull-down device connection capabilities. The
request input lines used by the FADC module are controlled by the port input/output
control registers P1_IOCR0 and P7_IOCR0.
After reset, for the external request inputs the input function with a pull-up device is
selected. For reference, the P1_IOCR0 and P7_IOCR0 functionality is shown on the
next page in respect to the FADC external request inputs.
DISCLK 31 rwh Disable Clock
Hardware controlled disable for f
FADC
signal.
0 10,
[27:26]
rw Reserved
Read as 0; should be written with 0.
P1_IOCR0
Port 7 Input/Output Control Register 0
(10
H
) Reset Value: 2020 2020
H
31 28 23 20 15 12 7 4 0
PC3 0 PC2 0PC10PC00
rw r rw rrwrrwr
Field Bits Type Description
PC0,
PC1
[7:4],
[15:12]
rw Port Output Control for Port 1 Pins 0-3
1)
These bit fields determine the output port
functionality:
Port input/output control for P1.0/REQ0
Port input/output control for P1.1/REQ1
Field Bits Type Description
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