TC1796
System Units (Vol. 1 of 2)
Introduction
User’s Manual 1-17 V2.0, 2007-07
Intro, V2.0
1.3.1.2 High-Speed Synchronous Serial Interfaces
Figure 1-3 shows a global view of the Synchronous Serial Interface (SSC).
Figure 1-3 General Block Diagram of the SSC Interface
The SSC supports full-duplex and half-duplex serial synchronous communication up to
37.5 MBaud (@ 75 MHz module clock) with Receive and Transmit FIFO support. The
serial clock signal can be generated by the SSC itself (Master Mode) or can be received
from an external master (Slave Mode). Data width, shift direction, clock polarity and
phase are programmable. This allows communication with SPI-compatible devices.
Transmission and reception of data are double-buffered. A shift clock generator provides
the SSC with a separate serial clock signal. One slave select input are available for Slave
Mode operation. Eight programmable slave select outputs (chip selects) are supported
in Master Mode.
Note: The SSC0 contains an 8-stage Receive and Transmit FIFO. The SSC1 does not
provide any FIFO functionality.
Features
• Master and Slave Mode operation
– Full-duplex or half-duplex operation
– Automatic pad control possible
• Flexible data format
– Programmable number of data bits: 2 to 16 bits
– Programmable shift direction: LSB or MSB shift first
SLSI
MCB05575
SSC
Module
(Kernel)
SLSO[7:0]
MRST
MTSR
SCLK
Port
Control
MRSTB
MTSR
Master
SLSI[7:1]
SLSO[7:0]
MRSTA
MTSRB
MRST
MTSRA
SCLKB
SCLK
SCLKA
Slave
Slave
Master
Slave
Master
SSC Enabled
M/S Selected
Clock
Control
Address
Decoder
Interrupt
Control
f
SSC
EIR
TIR
RIR
f
CLC
To DMA
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