TC1796
System Units (Vol. 1 of 2)
CPU Subsystem
User’s Manual 2-2 V2.0, 2007-07
CPU, V2.0
2.2 Central Processing Unit Features
The 150 MHz TriCore TC1796 CPU includes:
Architecture
• 32-bit load/store architecture
• 4 Gbyte address range (2
32
)
• 16-bit and 32-bit instructions for reduced code size
• Data types:
– Boolean, integer with saturation, bit array, signed fraction, character, double-word
integers, signed integer, unsigned integer, IEEE-754 single-precision floating point
• Data formats:
– Bit, byte (8-bit), half-word (16-bit), word (32-bit), double-word (64-bit)
• Byte and bit addressing
• Little-endian byte ordering for data, memory and CPU registers
• Multiply and Accumulate (MAC) instructions:
– Dual 16 x 16, 16 x 32, 32 x 32
• Saturation integer arithmetic
• Packed data
• Addressing modes:
– Absolute, circular, bit reverse, long + short, base + offset with pre and post-update
• Instruction types:
– Arithmetic, address arithmetic, comparison, address comparison, logical, MAC,
shift, coprocessor, bit logical, branch, bit field, load/store, packed data, system
• General Purpose Register Set (GPRS):
– Sixteen 32-bit data registers
– Sixteen 32-bit address registers
– Three 32-bit status and program counter registers (PSW, PC, PCXI)
• Core Debug support (OCDS):
– Level 1 and 2, supported in conjunction with the CPS block
– Level 3, supported
Implementation
• Most instructions executed in 1 cycle
• Branch instructions in 1, 2 or 3 cycles (using branch prediction)
• Shadow registers for fast context switch
• Automatic context save-on-entry and restore-on-exit for: subroutine, interrupt, trap
• Two memory protection register sets
• Dual instruction issuing (in parallel into Integer Pipeline and Load/Store Pipeline)
• Third pipeline for loop instruction only (zero overhead loop)
• Optional floating point instruction set implemented
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