TC1796
Peripheral Units (Vol. 2 of 2)
Synchronous Serial Interface (SSC)
User’s Manual 20-21 V2.0, 2007-07
SSC, V2.1
•SLSI= 1: SSC slave is not selected.
– The slave receive input signals MTSRA or MTSRB are connected to MTSRI,
depending on PISEL.SRIS (Slave Mode receive input select).
– MRST is driven with the logic level of bit PISEL.STIP (slave transmit idle state).
– SCLKI is driven with the logic level of CON.PO (clock polarity control).
•SLSI= 0: SSC is selected as slave.
– The slave receive input signals MTSRA or MTSRB are connected to MTSRI,
depending on PISEL.SRIS (Slave Mode receive input select).
– MRST is directly driven with the slave transmit output signal MRSTI.
– The slave clock input signals SCLKA or SCLKB are connected to SCLKI,
depending on PISEL.SCIS (Slave Mode clock input select).
20.1.2.11 Slave Select Output Generation Unit
In Master Mode, the slave select output generation unit of the SSC automatically
generates up to eight slave select output lines for serial transmit operations. The slave
select output generation unit further makes it possible to adjust the chip select timing
parameters. The active/inactive state of a slave select output as well as the
enable/disable state can be controlled individually for each slave select output (see
Figure 20-12). The basic slave select output timing is shown in Figure 20-11, assuming
a low active level of the SLSOn lines.
Figure 20-11 SSC Slave Select Output Timing
Last
Bit
1.Bit
InvalidInvalid
MCT05786_mod
SLSOn
t
SLSOI
MTSR
Slave Select Output Period
Data Frame
Note: This timing example is based on the following setup: CON.PH = 0; CON.PO = 1
MRST
SCLK
Sample points
1.Bit 1.Bit
1.Bit
Last
Bit
t
SLSOL
t
SCLK
t
SLSOT
t
SLSOL
t
SLSOACT
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