TC1796
System Units (Vol. 1 of 2)
General Purpose I/O Ports and Peripheral I/O Lines
User’s Manual 10-46 V2.0, 2007-07
Ports, V2.0
10.6.3.1 Port 3 Pad Driver Mode Register and Pad Classes
The Port 3 pad driver mode register contains two bit fields that determine the pad driver
mode (output driver strength and slew rate) of Port 3 line groups. The Port 3 port lines
are all of pad class A1 (see also Figure 10-7).
P3_PDR
Port 3 Pad Driver Mode Register (40
H
) Reset Value: 0000 0000
H
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
r
1514131211109876543210
0 PD10PD0
rrwrrw
Field Bits Type Description
PD0 [2:0] rw Pad Driver Mode for P3.[7:0]
(Class A1 pads; for coding see Page 10-11)
PD1 [6:4] rw Pad Driver Mode for P3.[15:8]
(Class A1 pads; for coding see Page 10-11)
0 3,
[31:7]
r Reserved
Read as 0; should be written with 0.
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