TC1796
System Units (Vol. 1 of 2)
Direct Memory Access Controller
User’s Manual 12-32 V2.0, 2007-07
DMA, V2.0
12.1.8.4 Wrap Buffer Interrupts
Each DMA channel mn is able to generate a wrap buffer interrupt for source buffer or
destination buffer overflow. Further details on the pattern detection are described in
Section 12.1.9.
A wrap source buffer interrupt of DMA channel nm is indicated by status flag
WRPSR.WRPSmn. A wrap destination buffer interrupt of DMA channel nm is indicated
by the status flag WRPSR.WRPDmn. Both interrupt status flags can be cleared by
software when bit INTCR.CWRPmn (or CHRSTR.CHmn becomes set. The wrap source
buffer interrupt is enabled when bit CHICRmn.WRPSE is set. The wrap destination
buffer interrupt is enabled when bit CHICRmn.WRPDE is set. The two interrupts for wrap
source buffer and wrap destination buffer are OR-ed together to one common wrap
buffer interrupt of DMA channel mn that can be directed to one of the interrupt outputs
SR[15:0]
1)
by setting the wrap buffer interrupt pointer CHICRmn.WRPP with a
corresponding value. Note that the pattern match should not be enabled while a wrap
buffer interrupt is enabled for the same channel.
Figure 12-22 DMA Wrap Buffer Interrupts
1) In the TC1796, only SR[7:0] are connected to interrupt nodes.
Wrap Source
Buffer
Interrupt mn
INTCR
Clear
WRPSR
Clear
WRPSR
Wrap Destination
Buffer
Interrupt mn
m = 0- 1, n = 0- 7
Set
CHRSTR
CHmn
WRPSmn
CWRPmn
WRPDmn
WRPSE
CHICRmn
WRPDE
CHICRmn
MCA05699_mod
WRPP
CHICRmn
4
≥1
Set
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