TC1796
System Units (Vol. 1 of 2)
Direct Memory Access Controller
User’s Manual 12-110 V2.0, 2007-07
DMA, V2.0
12.4 Memory Checker Module
12.4.1 Functional Description
The Memory Checker Module (MCHK) makes it possible to check the data consistency
of memories. Any SPB bus master may access the memory checker. Preferable the
DMA controller does it as described hereafter. It uses 8-bit, 16-bit, or 32-bit DMA moves
to read from the selected address area and to write the value read in a memory checker
input register. With each write operation to the memory checker input register, a
polynomial checksum calculation is triggered and the result of the calculation is stored
in the memory checker result register.
In order to start a memory check sequence, the memory checker result register must be
initialized (e.g. written with FFFF
H
or with a desired start value) and a DMA transaction
has to be set up (start address, length, etc.). When programming the DMA channel for
the memory checker with CHCRmn.RROAT = 1, one DMA transfer request (software or
hardware triggered) starts the DMA transaction.
At the read move operations of the DMA transaction, data is always read from the
memory and then written into the memory checker input register for the polynomial
checksum calculation. At the end of the transaction (CHSRmn.TCOUNT = 0), an
interrupt can be generated by the DMA channel (if CHCRmn.RROAT = 1), and the
memory checker result register can be read out by software.
The memory checker uses the standard Ethernet polynomial, which is given by:
G
32
= x
32
+ x
26
+ x
23
+ x
22
+ x
16
+ x
12
+ x
11
+ x
10
+ x
8
+ x
7
+ x
5
+ x
4
+ x
2
+ x +1 (12.1)
Note: Although the polynomial above is used for generation, the generation algorithm
differs from the one that is used by the Ethernet protocol.
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