TC1796
Peripheral Units (Vol. 2 of 2)
Analog-to-Digital Converter (ADC)
User’s Manual 25-52 V2.0, 2007-07
ADC, V2.0
Master Functionality
After an arbitration winner is detected, the Synchronized Injection Mode bit field
CHCONn.SYM is evaluated. If this bit field is configured either for sync-wait
(CHCONn_SYM = 01
B
) or cancel-sync-repeat (CHCONn.SYM = 10
B
) functionality, a
synchronized-request is generated for the slave ADC module. A synchronized request
means setting bit SYSTAT.SYREQ in the slave’s register.
Table 25-11 Master-Slave Functionality and Control
Functionality
during Sync.
Conversion
Controls Description
Master CHCONn.SYM Selects either sync-wait or cancel-sync-repeat
feature
STAT.REQSY Status bit indicating master functionality
STAT.IENREQ Status bit is driven by master to indicate that the
master finished its synchronized conversion
STAT.IENPAR Status bit is driven by slave to indicate that the
slave finished its synchronized conversion
Slave SYSTAT.SYREQ Status bit is driven by master to request the slave
for a synchronized conversion
SYSTAT.CHNRSY Status bit field is driven by master to indicate the
channel to be converted for a synchronized
conversion
SYSTAT.RES Status bit field is driven by master to indicate the
resolution for a synchronized conversion
SYSTAT.EMUX Status bit field is driven by master to indicate the
external multiplexer control info for a
synchronized conversion
SYSTAT.GRPS Status bit field is driven by master to indicate the
analog input multiplexer group select state for a
synchronized conversion
SYSTAT.CSREN Status bit is driven by master to indicate whether
sync-wait or cancel-sync-repeat feature was
selected in the master
Master/Slave STAT.SYMS Status bit to indicate that both modules
requested a synchronized conversion at the
same time for the same channel
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