TC1796
System Units (Vol. 1 of 2)
Direct Memory Access Controller
User’s Manual 12-89 V2.0, 2007-07
DMA, V2.0
The Destination Address Register contains the 32-bit destination address. If a DMA
channel is active, DADRmx is updated continuously (if programmed) and shows the
actual destination address that is used for write moves within DMA transfers.
A write to DADRmx is executed directly only when the DMA channel mx is inactive
(CHSRmx.TCOUNT = 0 and TRSR.CHmx = 0). If DMA channel mx is active when
writing to DADRmx, the source address will not be written into DADRmx directly but will
be buffered in the shadow register SHADRmx until the start of the next DMA transaction.
During this shadowed address register operation, bit field ADRCRmx.SHCT must be set
to 10
B
.
DMA_DADR0x (x = 0-7)
DMA Channel 0x Destination Address Register
(x*20
H
+94
H
) Reset Value: 0000 0000
H
DMA_DADR1x (x = 0-7)
DMA Channel 1x Destination Address Register
(x*20
H
+194
H
) Reset Value: 0000 0000
H
31 0
DADR
rwh
Field Bits Type Description
DADR [31:0] rwh Destination Address
This bit field holds the actual 32-bit destination address
of DMA channel mx that is used for write moves.
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