TC1796
Peripheral Units (Vol. 2 of 2)
Fast Analog-to-Digital Converter (FADC)
User’s Manual 26-17 V2.0, 2007-07
FADC, V2.0
Intermediate Result Calculation
When the continuous conversion of channel x has been started, the Current Result
Register CRRn (n = filter block number) is set to 0. Each following conversion result is
added to the content of CRRn until a programmable number of conversion results have
been summed up in CRRn. At that point, the calculation of the next final result value is
triggered. In the example of Figure 26-8, one intermediate result is built by the sum of
four conversion results (FCRn.ADDL = 011
B
). The state of the current result calculation
cycle is indicated by the addition counter AC which is located in register CRRn.
Final Result Calculation
The calculation of a final result is always started after an intermediate result calculation
cycle has been finished. This new intermediate result (stored in CRRn) plus the contents
of the intermediate registers are added according to:
• Filter 0: FRR0 := CRR0 + IRR10 + IRR20 + IRR30
• Filter 1: FRR1 := CRR1 + IRR11
Therefore, FRRn always contains the sum of maximum four (for filter block 0) or two (for
filter block 1) intermediate results. Bit field FCRn.MAVL determines the number of
intermediate results that are used for the final result calculation.
After a final result calculation, the old contents of IRR20 are transferred into IRR30 and
IRR10 are transferred into IRR20 (for filter block 0). In filter block 1, the contents of CRR1
are stored in IRR11. The old contents of IRR30 or IRR11 are lost. Finally, the value of
CRRn is transferred as intermediate result into the intermediate result register IRR1n.
Thereafter, the CRRn register is set to 0 for the next current result calculation cycle.
Each update of a result register FRRn with a new final result value generates a filter
block n service request. During a final result calculation phase (phase C in Figure 26-8),
the contents of the FRRn registers change. Therefore, it is recommended to read a final
result from the FRRn registers immediately (for example, by a DMA operation) after a
corresponding interrupt request flag CRSR.IRQFn has been set.
Filter Control Parameters
The Filter n Control Register FCRn contains several parameters that determine the
operation of filter n:
• FCRn.INSEL:
This parameter selects the channel(s) whose conversion results are used as filter n
input. A single channel, all four channels, or the final result of filter 0 (for filter 1
concatenation) can be selected. The filter n operation can also be stopped via
FCRn.INSEL.
• FCRn.ADDL:
This parameter determines how many conversion results are added in filter n to
calculate one intermediate result. FCRn.ADDL is loaded into CRRn.AC at the start of
To Next Page
Loading...
Need help?
General