TC1796
System Units (Vol. 1 of 2)
Peripheral Control Processor (PCP)
User’s Manual 11-124 V2.0, 2007-07
PCP, V2.0
MSTEP32 R1, R4 ;Perform one MSTEP32 instruction
;(8 bit multiply)
After this sequence, R0 holds the result, R1 is left unchanged (right rotated by RR
instruction then left rotated by MSTEP32 instruction), and R4 is unchanged. The result
is only valid if there is no overflow (i.e. the product of the 8-bit number in R1 multiplied
by the 32-bit number in R4 can be contained within 32 bits). It is the user’s responsibility
to ensure that this is the case. The overflow condition cannot be detected after execution
of the multiply sequence.
Example of a 32 × 16 bit multiply (R3 × R2) yielding a 32 bit result
(R3 = 32 bit, R2 = 16 bit):
RR R2, 8 ;Perform two 8 bit rotations
;(RR instructions) to get original
;least significant 16 bits into
;most significant 16 bits
RR R2, 8
MINIT R2, R3 ;Initialize ready for multiply
MSTEP32 R2, R3 ;Perform two MSTEP32 instructions
;(16 bit multiply)
MSTEP32 R2, R3
After this sequence, R0 holds the result, R2 is left unchanged (right rotated by two RR
instructions, then left rotated by two MSTEP32 instructions), R3 is unchanged. The
comment above regarding overflow also applies to this sequence.
Example of a 32 × 32 bit multiply (R5 × R2) yielding a 64 bit result
(R5 = 32 bit, R2 = 32 bit):
MINIT R2, R5 ;Initialize ready for multiply
MSTEP64 R2, R5 ;Perform 4 MSTEP64 instructions
;(64-bit multiply)
MSTEP64 R2, R5
MSTEP64 R2, R5
MSTEP64 R2, R5
After this sequence R0 and R2 hold the result (most significant word in R0, least
significant word in R2), R5 is unchanged. There is no possibility of overflow as the result
of 32 × 32 bits can always be contained in 64 bits.
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