TC1796
System Units (Vol. 1 of 2)
Introduction
User’s Manual 1-31 V2.0, 2007-07
Intro, V2.0
Figure 1-9 General Block Diagram of the ADC Module
Each of the two ADC modules, ADC0 and ADC1 has 16 analog input channels. An
analog multiplexer selects the input line for the analog input channels from among
32 analog inputs. Additionally, an external analog multiplexer can be used for analog
input extension. External Clock control, address decoding, and service request
(interrupt) control are managed outside the ADC module kernel. A synchronization
bridge is used for synchronization of two ADC modules. External trigger conditions are
controlled by an External Request Unit. This unit generates the control signals for auto-
scan control (ASGT), software trigger control (SW0TR, SW0GT), the event trigger
control (ETR, EGT), queue control (QTR, QGT), and timer trigger control (TTR, TGT).
Interrupt
Control
Clock
Control
Address
Decoder
ADC
Module
Kernel
f
ADC
SR[7:0]
Port
Control
MCB05581
Synchronization Bridge
V
AGND
V
DD
V
SS
V
DDM
V
AREF
V
SSM
Group 1
f
CLC
Group 0
External
Request
Unit
ASGT
SW0TR, SW0GT
ETR, EGT
QTR, QGT
TTR, TGT
EMUX0
EMUX1
GRPS
To DMA
EMUX0
EMUX1
GRPS
AIN0
AIN15
AIN16
AIN31
Analog Input Multiplexer
16 Analog Input Channels
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