TC1796
System Units (Vol. 1 of 2)
Direct Memory Access Controller
User’s Manual 12-52 V2.0, 2007-07
DMA, V2.0
The bits in the Transaction Request State Register indicates which DMA channel is
processing a request, and which DMA channel has hardware transaction requests
enabled.
DMA_TRSR
DMA Transaction Request State Register
(014
H
) Reset Value: 0000 0000
H
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HT
RE
17
HT
RE
16
HT
RE
15
HT
RE
14
HT
RE
13
HT
RE
12
HT
RE
11
HT
RE
10
HT
RE
07
HT
RE
06
HT
RE
05
HT
RE
04
HT
RE
03
HT
RE
02
HT
RE
01
HT
RE
00
rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh
1514131211109876543210
CH
17
CH
16
CH
15
CH
14
CH
13
CH
12
CH
11
CH
10
CH
07
CH
06
CH
05
CH
04
CH
03
CH
02
CH
01
CH
00
rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh
Field Bits Type Description
CH0x
(x = 0-7)
xrhTransaction Request State of DMA Channel 0x
0
B
No DMA request is pending for channel 0x.
1
B
A DMA request is pending for channel 0x.
CH0x is cleared when a pattern match is detected.
CH1x
(x = 0-7)
8+x rh Transaction Request State of DMA Channel 1x
0
B
No DMA request is pending for channel 1x.
1
B
A DMA request is pending for channel 1x.
CH1x is cleared when a pattern match is detected.
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