TC1796
System Units (Vol. 1 of 2)
Direct Memory Access Controller
User’s Manual 12-53 V2.0, 2007-07
DMA, V2.0
HTRE0x
(x = 0-7)
16+x rh Hardware Transaction Request Enable State of DMA
Channel 0x
0
B
Hardware transaction request for DMA Channel
0x is disabled. An input DMA request will not
trigger the channel 0x.
1
B
Hardware transaction request for DMA Channel
0x is enabled. The transfers of a DMA transaction
are controlled by the corresponding channel
request line of the DMA requesting source.
HTRE0x is set to 0 when CHSR0x.TCOUNT is
decremented and CHSR0x.TCOUNT = 0. HTRE0x can
be enabled and disabled with HTREQ.ECH0x or
HTREQ.DCH0x.
HTRE0x is cleared when a pattern match is detected.
HTRE1x
(x = 0-7)
24+x rh Hardware Transaction Request Enable State of DMA
Channel 1x
0
B
Hardware transaction request for DMA Channel
1x is disabled. An input DMA request will not
trigger the channel 1x.
1
B
Hardware transaction request for DMA Channel
1x is enabled. The transfers of a DMA transaction
are controlled by the corresponding channel
request line of the DMA requesting source.
HTRE1x is set to 0 when CHSR1x.TCOUNT is
decremented and CHSR1x.TCOUNT = 0. HTRE1x can
be enabled and disabled with HTREQ.ECH1x or
HTREQ.DCH1x.
HTRE1x is cleared when a pattern match is detected,
Field Bits Type Description
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