Infineon Technologies TC1796 - Page 1653

TC1796
Peripheral Units (Vol. 2 of 2)
Micro Link Interface (MLI)
User’s Manual 23-144 V2.0, 2007-07
MLI, V2.0
The coding of bit fields SIZE1 and SLICE1 for the SRAM sub-range access protection
(with address translation from E800 to C000) are coded as shown in Table 23-17.
101
B
4 sub-ranges of
2Kbytes
XXX00
B
XXX01
B
XXX10
B
XXX11
B
F010 A000
H
to F010 A7FF
H
F010 A800
H
to F010 AFFF
H
F010 B000
H
to F010 B7FF
H
F010 B800
H
to F010 BFFF
H
110
B
2 sub-ranges of
4Kbytes
XXXX0
B
XXXX1
B
F010 A000
H
to F010 AFFF
H
F010 B000
H
to F010 BFFF
H
111
B
8 Kbytes XXXXX
B
F010 A000
H
to F010 BFFF
H
Table 23-17 SRAM Address Protection Sub-Range Definitions
SIZE1 Sub-Ranges SLICE1 Selected Address Range
000
B
32 sub-ranges of
512 bytes
00000
B
00001
B
…
11111
B
E800 0000
H
to E800 01FF
H
E800 0200
H
to E800 03FF
H
…
E800 3E00
H
to E800 3FFF
H
E800 4000
H
to E800 FFFF
H
is not selectable
001
B
32 sub-ranges of
1Kbyte
00000
B
00001
B
…
11111
B
E800 0000
H
to E800 03FF
H
E800 0400
H
to E800 07FF
H
…
E800 7C00
H
to E800 7FFF
H
E800 8000
H
to E800 FFFF
H
is not selectable
010
B
32 sub-ranges of
2Kbytes
00000
B
00001
B
…
11111
B
E800 0000
H
to E800 07FF
H
E800 0800
H
to E800 0FFF
H
…
E800 F800
H
to E800 FFFF
H
011
B
16 sub-ranges of
4Kbytes
X0000
B
X0001
B
…
X1111
B
E800 0000
H
to E800 0FFF
H
E800 1000
H
to E800 1FFF
H
…
E800 F000
H
to E800 FFFF
H
100
B
8 sub-ranges of
8Kbytes
XX000
B
XX001
B
…
XX111
B
E800 0000
H
to E800 1FFF
H
E800 2000
H
to E800 3FFF
H
…
E800 E000
H
to E800 FFFF
H
Table 23-16 DPRAM Address Protection Sub-Range Definitions (cont’d)
SIZE0 Sub-Ranges SLICE0 Selected Address Range