TC1796
Peripheral Units (Vol. 2 of 2)
Micro Second Channel (MSC)
User’s Manual 21-9 V2.0, 2007-07
MSC, V2.0
Data Frames
A data frame has two active phase parts, SRL active phase and SRH active phase. The
number of bits that are transmitted can be programmed separately for each of these two
phases. Bit field DSC.NDBL determines the number of SRL bits that are transmitted
during the SRL active phase and DSC.NDBH determines the number of SRH bits that
are transmitted during the SRH active phase.
SRL and SRH active phases can start with a low-level selection bit when enabled by bits
DSC.ENSELL or DSC.ENSELH.
During the SRL active phase of a data frame, the enable output signal ENL becomes
active and during the SRH active phase of a data frame, the enable output signal ENH
becomes active. The enable output signal ENC remains inactive.
The length of the data frame’s passive phase is variable and is defined by bit field
DSC.PPD. It can be within a range of 2 × t
FCL
up to 31 × t
FCL
. The diagram shown in
Figure 21-5 assumes that the FCL clock is only generated during the active phase of the
data frame (OCR.CLKCTRL = 0).
Table 21-2, Table 21-3, and Table 21-4 show the definitions of the five data frame
parameters that determine the layout of the data frame.
Figure 21-6 Data Frame Layout
MCT05800
SRL.0 SRL.n
Passive Phase
FCL
SO
ENH
ENL
t
FCL
SRH.00
Data Frame
Active Phase
Length defined
by DSC.PPD
0SRL.m
Length defined by
DSC.NDBH
Length defined by
DSC.NDBL
SRL Active Phase SRH Active Phase
1) Interrupt generation possible.
1)
1)
Selection Bit
Selection Bit
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