TC1796
Peripheral Units (Vol. 2 of 2)
General Purpose Timer Array (GPTA)
User’s Manual 24-29 V2.0, 2007-07
GPTA, V2.0
Figure 24-18 Block Diagram of Digital PLL Cell
The desired input signal is selected by programming bit field PLLCTR.MUX. The number
of output pulses to be generated within one input signal period must be stored in the
microtick register PLLMTI and (coded in 2-complement data format) in the step register
PLLSTP. The PLLREV reload register must be programmed with a reload value. This
reload value is calculated by subtracting the number of output pulses to be generated
within one input signal period from the input signal’s period length (measured in number
of f
GPTA
clocks). An automatic compensation of an input signal acceleration or
deceleration is enabled by setting bit PLLCTR.AEN to 1 (Automatic End Mode). After
disabling the Automatic End Mode, the PLL continuously generates output pulses
without synchronization to an input signal edge.
When the counter for the number of remaining output signal pulses PLLCNT decrements
to zero, the PLL service request flag is set. Additionally, a service request signal PLLSR
will be generated if the control register bit PLLCTR.REN is set.
MCB05927
Input
MUX
16
MTI (Microtick Value)
PLLMTI
CNT (Microtick Counter)
PLLCNT
REV (Reload Value)
PLLREV
STP (Step Value)
PLLSTP 2-Complement
MUX
DTR (Delta Value)
PLLDTR
Sign Bit
ADD Unit
PLL Signal
Uncompensated PLL Signal
Service Request
PLL
Control
Logic
REN
PLLCTR
MUX
&
Load
2
24
16
24
DCM0
DCM1
DCM2
DCM3
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