Infineon Technologies TC1796 User Manual

TC1796
System Units (Vol. 1 of 2)
On-Chip System Buses and Bus Bridges
User’s Manual 6-43 V2.0, 2007-07
Buses, V2.0
CONCOM0 12 rw Grant and Address Trigger Relation
0
B
Grant trigger condition and the address trigger
condition are combined with a logical OR for
further control.
1
B
The grant trigger condition and the address
trigger condition are combined with a logical
AND for further control (see Figure 6-12).
CONCOM1 13 rw Address 1 and Address 2 Trigger Relation
0
B
Address 1 trigger condition and address 2
trigger condition are combined with a logical
OR for further control.
1
B
Address 1 trigger condition and address 2
trigger condition are combined with a logical
AND for further control (see Figure 6-12).
CONCOM2 14 rw Address and Signal Trigger Relation
0
B
Address trigger condition and signal trigger
condition are combined with a logical OR for
further control.
1
B
Address trigger condition and the signal trigger
condition are combined with a logical AND for
further control (see Figure 6-12).
ONG 16 rw Grant Trigger Enable
0
B
No grant debug event trigger is generated.
1
B
The grant debug event trigger is enabled and
generated according the settings of register
DBGRNT (see Figure 6-11).
ONA1 [21:20] rw Address 1 Trigger Control
00
B
No address 1 trigger is generated.
01
B
An address 1 trigger event is generated if the
FPI Bus address is equal to DBADR1.
10
B
An address 1 trigger event is generated if
FPI Bus address is greater or equal to
DBADR1.
11
B
same as 00
B
.
See also Figure 6-9.
Field Bits Type Description

Infineon Technologies TC1796 Specifications

General

Brand	Infineon Technologies
Model	TC1796
Category	Controller
Language	English