Infineon Technologies TC1796 - Page 337

TC1796
System Units (Vol. 1 of 2)
On-Chip System Buses and Bus Bridges
User’s Manual 6-44 V2.0, 2007-07
Buses, V2.0
ONA2 [25:24] rw Address 2 Trigger Control
00
B
No address 2 trigger is generated.
01
B
An address 2 trigger event is generated if the
FPI Bus address is equal to DBADR2.
10
B
An address 2 trigger event is generated if
FPI Bus address is greater or equal to
DBADR2.
11
B
same as 00
B
.
See also Figure 6-9.
ONBOS0 28 rw Opcode Signal Status Trigger Condition
0
B
A signal status trigger is generated for all
FPI Bus opcodes except a “no operation”
opcode.
1
B
A signal status trigger is generated if the
FPI Bus opcode matches the opcode as
defined in DBBOS.OPC (see Figure 6-10).
ONBOS1 29 rw Supervisor Mode Signal Trigger Condition
0
B
The signal status trigger generation for the
FPI Bus supervisor mode signal is disabled.
1
B
A signal status trigger is generated if the
FPI Bus supervisor mode signal state is equal
to the value of DBBOS.SVM (see Figure 6-10).
ONBOS2 30 rw Write Signal Trigger Condition
0
B
The signal status trigger generation for the
FPI Bus write signal is disabled.
1
B
A signal status trigger is generated if the
FPI Bus write signal state is equal to the value
of DBBOS.WR (see Figure 6-10).
ONBOS3 31 rw Read Signal Trigger Condition
0
B
The signal status trigger generation for the
FPI Bus read signal is disabled.
1
B
A signal status trigger is generated if the
FPI Bus read signal state is equal to the value
of DBBOS.RD (see Figure 6-10).
Field Bits Type Description