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Infineon Technologies TC1796 User Manual

Infineon Technologies TC1796
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TC1796
System Units (Vol. 1 of 2)
On-Chip System Buses and Bus Bridges
User’s Manual 6-45 V2.0, 2007-07
Buses, V2.0
0 [3:2],
[11:5],
15,
[19:17],
[23:22],
[27:26]
r Reserved
Read as 0; should be written with 0.
SBCU_DBGRNT
SBCU Debug Grant Mask Register (34
H
) Reset Value: 0000 FFFF
H
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
r
1514131211109876543210
1 CBL
DMA
L
LFI
DMA
H
PCP 1 CBH
rw rw rw rw rw rw rw rw
Field Bits Type Description
CBH 0rwCerberus Grant Trigger Enable, High Priority
0
B
FPI Bus transactions on SPB with high-priority
Cerberus as bus master are enabled for grant
trigger event generation.
1
B
FPI Bus transactions on SPB with high-priority
Cerberus as bus master are disabled for grant
trigger event generation.
1 [2:1],
[15:8]
rw Reserved
Read as 1 after reset; reading these bits will return the
value last written.
PCP 3rwPCP Grant Trigger Enable
0
B
FPI Bus transactions on SPB with PCP as bus
master are enabled for grant trigger event
generation.
1
B
FPI Bus transactions on SPB with PCP as bus
master are disabled for grant trigger event
generation.
Field Bits Type Description

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Infineon Technologies TC1796 Specifications

General IconGeneral
BrandInfineon Technologies
ModelTC1796
CategoryController
LanguageEnglish